I am trying to implement the minsoc core along with its Ethernet MAC core on a Xilinx ML505 Virtex-5 board. I made a change in the "eth_sparma_256x32.v" file, which is a buffer of the ethmac core,because it was using RAMB4 BRAMs which are not supported in Virtex-5. Instead I used RAMB16.

I can configure the phy chip and initialize it (reset and set the communication speed for 100 and 10 Mbps) through my software but I can't receive or transmit any data. I can also see that I can correctly initialize all the registers of the phy chip.

I took the sw from the ORPSoC v2 project where they have used the ML501 board. Also the datasheet for the phy chip for ML501 and ML505 Xilinx boards is not available (Marvell 88E1111).

Any help? Thanx!